The present invention relates to a CMOS IC/LSI, and particularly to a semiconductor integrated circuit which is capable of operating at higher speeds than conventional circuits.
The carrier mobility of an n-channel MOS transistor formed on a silicon crystalline surface is nearly a maximum when the device is formed on the surface of a semiconductor substrate of a plane azimuth (100) as taught in a patent (Japanese patent publication Kokoku No. 42-21976) invented by Ohno et al. Therefore, an MOS integrated circuit has heretofore been formed on the plane (100) or on a plane close thereto. As shown in FIG. 1, however, the measured carrier mobility of a p-channel MOS transistor is nearly minimal when the device is formed on the surface of the plane (100). With a MOS integrated circuit (hereinafter referred to as a CMOS IC) in which n-channel MOS transistors and p-channel MOS transistors are densely formed on the same substrate, the operating speed varies in equal proportion to the carrier mobility of transistors of both the n-and p-types. It is therefore obvious that the plane (100) on which the carrier mobility of the p-channel MOS transistor is nearly minimal, is not utilizable as an optimum plane azimuth for the CMOS IC's.